Frequency Counting Circuit

Circuit Diagram (Adobe PDF)

Frequency counter options

In order to accurately tune a bass, the instantaneous frequency of the resonating string needs to be known. There were several options considered for solving this problem. The first option was to use the HandyBoard's pulse accumulator on-board counter (Motorola M68HC11 Reference Manual, Section 11, page 11-8). The second option was to incorporate software code (polling) on the Handyboard. A third option was to use another programmable micro-controller with an on-board clock to calculate the frequency. The final option was to build a frequency calculation circuit (independent of the Handyboard). Due to project time constraints, learning Assembly Language to use the Handyboard's on-board pulse accumulator was eliminated. Polling also was dismissed due to the amount of processor time it would take to obtain an average period of the incoming signal. Using another programmable micro-controller to calculate frequency was not chosen because it seemed to be over-kill. So building a frequency calculation circuit was the chosen option.

Simple circuit walkthrough

In order to obtain an accurate frequency from the resonating string, the circuit was designed to calculate the period of four pulse cycles. The string signal is a sinuisoid that matches the played note's frequency. This input signal, from the instrument, goes through a signal conditioning circuit. The signal conditioning circuit first amplifies the input signal from approximately 20 mV peak-to-peak to approximately 10 V peak-to-peak. Then it low-pass filters the signal with a cutoff frequency of about 1950 Hz. The cutoff frequency was chosen because the highest frequency from a standard six-string guitar is 1318.510. The signal then passes through a peak detector, a comparator, and finally a half-wave rectifier. The result of the signal conditioning circuit is a 5 V square wave that oscillates at the frequency of the resonating string.

Obtaining the signal period

Now the task at hand is to obtain the period of four pulses. This is accomplished through the use of digital logic, timer/counters, and a latch. A 7-bit ripple counter is used to obtain the three pulses needed to trigger and reset the other IC chips. These other chips count the time in between periods. The theory behind the circuit is as follows. The first pulse of the four-pulse sequence starts a timer/counter. The timer/counter starts a separate timing pulse train with a period equal to a preset RC time constant. This time constant was set to approximately 500 ms. The 500 ms time constant was chosen based on the frequencies being tested. A bass guitar was used for the prototype. A bass operates in the frequency range of about 61 Hz to 196 Hz. The timer counter chip can count up to 255 timing pulses. The design calls for the averaging of four pulses, so there is a limit on the period of the timing pulses. The formula used to calculate the period of the timing pulses is: . The timer/counter continues to count timing pulses until it is reset. This count is output from the timer as an 8-bit binary number and sent to the latch. Next, the last pulse of the four-pulse sequence, from the original conditioned signal, is sent to the latch. This pulse tells the latch to hold the values from the counter. This number now held in the latch is the count of timing pulses from the timer/counter chip, and is representative of the period of four pulses. This number will be sent into the Handyboard. The Handyboard will take this number and calculate the frequency using the formula: . In order to accomplish this, three separate pulses must be derived from the original 5 V square wave conditioned signal: a trigger for the timer/counter, a reset for the timer counter, and a latch reset. This is accomplished through digital logic.

Chip control digital logic

As seen on the circuit diagram, the conditioned signal is input into a 7-bit binary ripple counter. The use of the ripple counter's output from Q1 (bit 0), Q2 (bit 1), Q3 (bit 2), NAND gates, and inverters are used to create the three input (as seen below in fig A) pulses needed to operate the timer/counter and latch IC chips (bottom three signals of fig A).

Circuit difficulties

There was a problem with the operation of the circuit. The latch holds the input values at the output when the reset is low, but when the rest is high; the output values follow the input values. This created a problem when the handyboard cycles through to read the next frequency. When the Handyboard read cycle occured while the latch is high, the instantaneous frequency was incorrect. To correct this, several checks were implemented. First the latch reset signal is sent into the Handyboard. This allows the Handyboard to check the value of the latch reset to determine if the reset is high or low. If it is high, the Handyboard will retain the previous frequency and not calculate a new one. It was seen that this did not totally remedy the error. It is hypothesized that because of the difference in sample rates the Handyboard was still reading values from the latch during a reset; so another safety check was applied. The output of the latch and the inverse latch signal were input into an AND gate. The result was if the reset was high the AND gate would output a low. The handyboard was then programmed not to recognize an all-low output. With the implementation of the two 'safety' checks, the output was a steady frequency output from the frequency circuit/Handyboard.